Cypress Semiconductor /psoc63 /PERI /PPU_GR[2] /ATT1

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Interpret as ATT1

Description

PPU region attributes 1 (master structure)

Fields

UR	See corresponding field for PPU structure with programmable address. Note that this register is constant ‘1’; i.e. user read accesses are ALWAYS allowed.
UW	See corresponding field for PPU structure with programmable address.
UX	See corresponding field for PPU structure with programmable address. Note that this register is constant ‘0’; i.e. user execute accesses are NEVER allowed.
PR	See corresponding field for PPU structure with programmable address. Note that this register is constant ‘1’; i.e. privileged read accesses are ALWAYS allowed.
PW	See corresponding field for PPU structure with programmable address.
PX	See corresponding field for PPU structure with programmable address. Note that this register is constant ‘0’; i.e. privileged execute accesses are NEVER allowed.
NS	See corresponding field for PPU structure with programmable address.
PC_MASK_0	See corresponding field for PPU structure with programmable address.
PC_MASK_15_TO_1	See corresponding field for PPU structure with programmable address.
REGION_SIZE	See corresponding field for PPU structure with programmable address. ‘7’: 256 B region
PC_MATCH	See corresponding field for PPU structure with programmable address.
ENABLED	See corresponding field for PPU structure with programmable address.

Links

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